module ysyx_23060189_EXU #(parameter xlen = 32) (
  // data: IDU <=> EXU
  input  wire [xlen-1:0] de_inst,
  input  wire [xlen-1:0] de_pc,
  input  wire [1:0]      de_PC_sel,
  input  wire [2:0]      de_Imm_sel,
  input  wire [3:0]      de_Alu_op,
  input  wire [1:0]      de_st_type,
  input  wire [2:0]      de_ld_type,
  input  wire [2:0]      de_br_type,
  input  wire [1:0]      de_A_sel,
  input  wire [1:0]      de_B_sel,
  input  wire [1:0]      de_wb_sel,
  input  wire [2:0]      de_csr_cmd,
  input  wire            de_wb_en,
  input  wire [4:0]      de_wb_addr,
  input  wire [xlen-1:0] de_rs1_data,
  input  wire [xlen-1:0] de_rs2_data,

  input  wire            de_valid,
  output wire            ex_ready,

  // data: EXU <=> MEU
  output wire [xlen-1:0] ex_inst,
  output wire [xlen-1:0] ex_pc,
  output wire [1:0]      ex_PC_sel,
  output wire [1:0]      ex_st_type,
  output wire [2:0]      ex_ld_type,
  output wire [1:0]      ex_wb_sel,
  output wire [2:0]      ex_csr_cmd,
  output wire            ex_wb_en,
  output wire            ex_br_taken,
  output wire [xlen-1:0] ex_Alu_out,
  output wire [4:0]      ex_wb_addr,
  output wire [xlen-1:0] ex_rs2_data,

  output wire            ex_valid,
  input  wire            me_ready
);

  wire [xlen-1:0] imm;

  assign ex_inst     = de_inst;
  assign ex_pc       = de_pc;
  assign ex_PC_sel   = de_PC_sel;
  assign ex_st_type  = de_st_type;
  assign ex_ld_type  = de_ld_type;
  assign ex_wb_sel   = de_wb_sel;
  assign ex_csr_cmd  = de_csr_cmd;
  assign ex_wb_en    = de_wb_en;
  assign ex_wb_addr  = de_wb_addr;
  assign ex_rs2_data = de_rs2_data;

  assign ex_valid = de_valid;
  assign ex_ready = 1;

  ysyx_23060189_ImmGen ImmGen(
    .inst(de_inst),
    .Imm_sel(de_Imm_sel),
    .imm(imm)
  );

  ysyx_23060189_Alu Alu(
    .imm(imm),
    .rs1_data(de_rs1_data),
    .rs2_data(de_rs2_data),
    .pc_out(de_pc),
    .Alu_op(de_Alu_op),
    .A_sel(de_A_sel),
    .B_sel(de_B_sel),
    .Alu_out(ex_Alu_out)
  );

  ysyx_23060189_BrCond BrCond(
    .br_type(de_br_type),
    .rs1_data(de_rs1_data),
    .rs2_data(de_rs2_data),
    .br_taken(ex_br_taken)
  );

endmodule
